Integrated circuit devices can include arrangements in which memory elements are utilized in conjunction with logic elements. For example, content addressable memory (CAM) devices can include CAM cells having one or more storage circuits that operate in conjunction with compare logic for determining whether one or more bits stored in the CAM cell match one or more compare data bits. Along these same lines, programmable logic devices can include storage circuits that store configuration information that can establish the functionality of corresponding logic circuit.
CAM devices can allow for a simultaneous search access to each entry stored in an associative memory cell array. Built-in compare circuitry within a CAM device can compare a specific pattern of bits, commonly known as a search key or comparand or compare data, against a large number of bit patterns stored in the associative memory cell array. Thus, an entire associative memory cell array can be searched essentially in parallel. Because of this parallel search capability, CAM devices are used in a growing number of applications, such as in network search engines (NSEs). NSEs can use CAMs to provide fast searches of a database, list, or pattern.
Typically, a memory cell array of a CAM device can be built from a large number of single CAM cells. A layout for a prior art single ternary CAM (TCAM) cell is shown in FIG. 11 and designated by the general reference character 1100. Generally, the conventional single TCAM cell can include a “stack” 1102 containing compare circuitry that is physically situated between two static random access memory (SRAM) cells (1104 and 1106). Each of the SRAM cells (1104 and 1106) can store bits of data (called X-value and Y-value). Such an X and Y value can be compared by transistors in the stack 1102 against external comparand data supplied to the TCAM cell via inputs. Such compare data is commonly labelled as compare data (CD) and an inverse compare data, or compare data “bar” (CDB). A stack 1102 can consist of four to six metal oxide semiconductor (MOS) transistors (in the example shown, n-channel transistors) placed adjacent to SRAM cells (1104 and 1106).
A conventional TCAM device, like that described above, can suffer from a number of problems, the most notable being a size limitation. Common TCAM applications can require a large depth or size in the number of entries (data) that may be formed in an array of memory cells. However, for a given TCAM memory cell array size, as width of the array (or the number of bits in each entry) increases, depth (or number of entries) can decrease correspondingly. Thus, to increase capacity of a memory cell array there is a need to increase the number of individual TCAM cells that can be formed in a single TCAM device. However, because each individual conventional TCAM cell can require a relatively large area on the substrate or die on which the TCAM device is formed, there is a relatively low limit to the size of a TCAM array, or number of TCAM cells, that can be implemented in a single TCAM device.
Accordingly, there is a need for some way of increasing the number of cells that may be included in memory cell array. For example, it would be desirable to arrive at a more compact layout that can reduce the area occupied by a memory/logic CAM cell on a die or substrate. It would also be desirable if such an approach was compatible with both “tapped” well and body bias approaches, in the event such a device is implemented in complementary device technology (e.g., CMOS).